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NTHS5445T1 Power MOSFET P-Channel ChipFETE
5.2 Amps, 8 Volts
Features
* Low RDS(on) for Higher Efficiency * Logic Level Gate Drive * Miniature ChipFET Surface Mount Package Saves Board Space
Applications
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* Power Management in Portable and Battery-Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
5.2 AMPS 8 VOLTS RDS(on) = 35 mW
S
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "7.1 "5.2 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C -2.1 "20 -1.1 "5.2 "3.7 A A W 5 secs Steady State G Unit V V A D P-Channel MOSFET
-8.0 "8.0
ChipFET CASE 1206A STYLE 1
-55 to +150
1. Surface Mounted on 1 x 1 FR4 Board.
PIN CONNECTIONS
D D D S
8 7 6 5 1 2 3 4
MARKING DIAGRAM
1 2 3 4 A5 8 7 6 5
D D D G
A5 = Specific Device Code
ORDERING INFORMATION
Device NTHS5445T1 Package ChipFET Shipping 3000/Tape & Reel
(c) Semiconductor Components Industries, LLC, 2005
February, 2005 - Rev. XXX
1
Publication Order Number: NTHS5445T1/D
NTHS5445T1
THERMAL CHARACTERISTICS
Characteristic Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State Maximum Junction-to-Foot (Drain) Steady State Symbol RthJA Typ 40 80 15 Max 50 95 20 Unit C/W
RthJF
C/W
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS VDS = VGS, ID = -250 A VDS = 0 V, VGS = "8.0 V VDS = -6.4 V, VGS = 0 V VDS = -6.4 V, VGS = 0 V, TJ = 85C On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) ID(on) rDS(on) () VDS v -5.0 V, VGS = -4.5 V VGS = -4.5 V, ID = -5.2 A VGS = -2.5 V, ID = -4.5 A VGS = -1.8 V, ID = -2.0 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = -1.1 A, di/dt = 100 A/s VDD = -4.0 V, RL = 4 ID ^ -1.0 A VGEN = -4.5 V 1 0 A, 4 5 V, RG = 6 - VDS = -4.0 V VGS = -4.5 V 4 0 V, 4 5 V, ID = -5.2 A - - - - - - - 17 2.8 2.6 15 45 110 65 30 26 - - 25 70 165 100 60 ns nC gfs VSD VDS = -5.0 V, ID = -5.2 A IS = -1.1 A, VGS = 0 V -0.45 - - - -20 - - - - - - - - - - 0.030 0.040 0.052 18 -0.8 - "100 -1.0 -5.0 - 0.035 0.047 0.062 - -1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit
2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.
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NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
20 VGS = 5 thru 2.5 V 16 ID,Drain Current (A) ID,Drain Current (A) 2V 16 20 TC = -55C 25C 125C
12 8 1.5 V 4 0 1V 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 3.0
12 8 4 0
0
0.5 1.0 1.5 2.0 VGS, Gate-to-Source Voltage (V)
2.5
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
0.10 r DS(on),On-Resistance ( ) 0.08 0.06 VGS = 2.5 V 0.04 0.02 0 VGS = 4.5 V VGS = 1.8 V C, Capacitance (pF)
3000 2500 2000 1500 1000 500 0 Coss Ciss
Crss 0 2 4 6 VDS, Drain-to-Source Voltage (V) 8
0
4
8 12 ID, Drain Current (A)
16
20
Figure 3. On-Resistance vs. Drain Current
Figure 4. Capacitance
5 VGS,Gate-to-Source Voltage (V) r DS(on),On-Resistance ( ) (Normalized) VDS = 4 V ID = 5.2 A
1.6 1.4 1.2 1.0 0.8 0.6 -50 VGS = 4.5 V ID = 5.2 A
4 3 2 1 0
0
4
8 12 Qg, Total Gate Charge (nC)
16
20
-25
0 25 50 75 100 TJ, Junction Temperature (C)
125
150
Figure 5. Gate Charge
Figure 6. On-Resistance vs. Junction Temperature
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NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
20 rDS(on), On-Resistance ( ) TJ = 150C I S, Source Current (A) 10 0.10 0.08 0.06 0.04 0.02 ID = 5.2 A
TJ = 25C
1
0
0.2
0.4 0.6 0.8 1.0 VDS, Drain-to-Source Voltage (V)
1.2
0
0
1 2 3 4 VGS, Gate-to-Source Voltage (V)
5
Figure 7. Source-Drain Diode Forward Voltage
Figure 8. On-Resistance vs. Gate-to-Source Voltage
50 40 Power (W) 30 20 10 0 10-3
0.4 0.3 V GS (th), Varience (V) 0.2 0.1 ID = 250 A
0.0
-0.1 -0.2 -50
-25
0
25 50 75 100 TJ, Temperature (C)
125
150
10-2
10 -1 1 Time (sec)
10
100
600
Figure 9. Threshold Voltage
Figure 10. Single Pulse Power
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NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) PDM t1 t2
t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600
Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 10
Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot
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NTHS5445T1
PACKAGE DIMENSIONS
CHIPFET CASE 1206A-01 ISSUE A
A
8 7 6 5
M K
5 6 3 7 2 8 1
S
1 2 3 4
B
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.15 0.30 0.45 0.55 BSC 5 NOM --- 1.80 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.012 0.018 0.022 BSC 5 NOM --- 0.071
L
G
D
J
C 0.05 (0.002)
STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8.
DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN
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NTHS5445T1
80 mil 18 mil 25 mil 68 mil 80 mil
26 mil
28 mil
26 mil
28 mil
Figure 13.
Figure 14.
BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 14. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
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NTHS5445T1
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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NTHS5445T1/D

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